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| TECHNICAL DATA KK4069UB Hex Inverter High-Voltage Silicon-Gate CMOS The KK4069UB types consist of six inverter circuits. These devices are intended for all general-purpose inverter applications where the mediumpower TTL-drive and logic-level-conversion capabilities of circuits such as the IW4049UB Hex Inverter/Buffers are not required. Each of the six inverters is a single stage * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 0.5 V min @ 5.0 V supply 1.0 V min @ 10.0 V supply 1.5 V min @ 15.0 V supply ORDERING INFORMATION KK4069UBN Plastic KK4069UBD SOIC TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs A L H PIN 14 =VCC PIN 7 = GND Output Y H L L - LOW voltage level H - HIGH voltage level 1 KK4069UB MAXIMUM RATINGS* Symbol VCC VIN IIN PD Ptot Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 10 500 500 100 -65 to +150 260 Unit V V mA mW mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 100 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK4069UB DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Test Conditions VOUT=0.5V VOUT=1.0 V VOUT=1.5V VOUT= VCC - 0.5 V VOUT= VCC - 1 V VOUT= VCC - 1.5 V VIN=GND V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit -55C 4.0 8.0 12.5 1.0 2.0 2.5 4.95 9.95 14.95 0.05 0.05 0.05 0.1 0.25 0.5 1.0 5.0 0.64 1.6 4.2 -2.0 -0.64 -1.6 -4.2 25C 4.0 8.0 12.5 1.0 2.0 2.5 4.95 9.95 14.95 0.05 0.05 0.05 0.1 0.25 0.5 1.0 5.0 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 125 C 4.0 8.0 12.5 1.0 2.0 2.5 4.95 9.95 14.95 0.05 0.05 0.05 1.0 7.5 15 30 150 0.36 0.9 2.4 mA -1.15 -0.36 -0.9 -2.4 Unit V VIL V VOH V VOL VIN= VCC V IIN ICC VIN= GND or VCC VIN= GND or VCC A A IOL VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V mA IOH Minimum Output VIN= GND or VCC High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 3 KK4069UB AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200k, Input tr=tf=20 ns) VCC Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Input A to Output Y (Figure 1) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance V 5.0 10 15 5.0 10 15 110 60 50 200 100 80 Guaranteed Limit -55C 25C 110 60 50 200 100 80 15 125C 110 80 80 200 100 80 Unit ns tTLH, tTHL ns CIN pF Figure 1. Switching Waveforms EXPANDED LOGIC DIAGRAM (1/6 of the Device) 4 KK4069UB N SUFFIX PLASTIC DIP (MS - 001AA) A 14 8 B 1 7 Dimension, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 10 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLANE G H H J M J K L M N NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 012AB) Dimension, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLANE H J F M J K M P R 8 0.25 0.25 6.2 0.5 NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. 5 |
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